ID:13252 Can't generate symbol/include/instantiation/component files for both "<name>" and "<name>" because they differ only in case; the symbol/include/instantiation/component file for "<name>" will overwrite the symbol/include/instantiation/component file for "<name>"

CAUSE: In a Verilog Design File (.v), there are two Module Declarations whose names differ only in case. When generating symbol/include/instantiation/component files for these two modules, the symbol file for the first module is overwritten by the symbol file for the second module.

ACTION: Change one of the Module Declarations so that their names are distinct regardless of case.