ID:13287 Verilog HDL or VHDL Synthesis Directive error at <location>: message-related synthesis directives are not allowed inside a scope

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you used a message-related synthesis directive. This directive is listed inside a module, entity, or architecture declaration. Message-related synthesis directive must appear outside the scope of a module, entity, or architecture.

ACTION: Move the synthesis directive outside the scope of the module, entity, or architecture. In VHDL, message-related synthesis directive should precede the entity's or architecture's context clause. In Verilog HDL, message-related synthesis directives should precede the module keyword.