ID:288015 Pin "<name>" is not declared in the port list of the Module Declaration for entity "<name>"

CAUSE: In the Verilog Quartus Mapping File (.vqm) that you generated with another EDA tool, the specified pin is not declared in the port list of the Module Declaration for the specified entity.

ACTION: Declare the specified port in the port list of the Module Declaration. In general, it is better to correct the source design file rather than the VQM File, and then regenerate the VQM File. If the error persists, contact the EDA tool vendor support for more information.