ID:288003 Module Declaration error: Module Declaration for module "<name>" cannot contain different ranges for port "<name>"

CAUSE: In the Verilog Quartus Mapping File (.vqm) that you generated with another EDA tool, the range specified for a port in a Module Declaration's list of ports is different from the range specified for the same port in an input, output, or inout declaration of the Module Declaration. You must use a consistent range for the port throughout the Module Declaration. This error may also have occurred if you created or edited a VQM File manually.

ACTION: Make sure the range for the port is the same in the list of ports and in the input, output, or inout declaration of the Module Declaration. Or, because you do not need to specify the range of the port in the list of ports, remove the range from the list of ports. In general, it is better to correct the source design file rather than the VQM File, and then regenerate the VQM File. If the error persists, contact the EDA tool vendor support for more information.