ID:288005 Port range "<name>" must match in Net Declaration and Module Declaration

CAUSE: In the Verilog Quartus Mapping File (.vqm) that you generated with another EDA tool, the range you specified for a port in a Net Declaration differs from the range you specified for the same port in a Module Declaration (for example, in an input declaration). The range of the port in the two declarations must be the same. This error may also have occurred if you created or edited a VQM File manually.

ACTION: Make sure the range for the port is the same in both declarations. In general, it is better to correct the source design file rather than the VQM File, and then regenerate the VQM File. If the error persists, contact the EDA tool vendor support for more information.