ID:201001 Generation of Verilog Test Bench File <name> for simulation was NOT successful

CAUSE: You attempted to generate the specified Verilog Test Bench File for simulation. However, the EDA Netlist Writer did not generate the Verilog Test Bench File.

ACTION: Refer to the messages that occur above this message in the Messages window or the Messages section of the Report Window for more information on why the EDA Netlist Writer could not generate the Verilog Test Bench File.