ID:265010 Current project contains Signal Tap IP VHDL design files copied from different version of Quartus Prime software

CAUSE: The current project contains Signal Tap IP VHDL design files from a different version of the Quartus Prime software that are not compatible with the current version of the Quartus Prime software, which can happen if you copy Signal Tap IP VHDL design files into one of the project directories or if you archived the project with megafunctions.

ACTION: Delete all VHDL design files matching sld*.vhd from the project directory and recompile the project.