ID:199000 Run Analysis and Synthesis with top-level entity name "<name>" or run I/O Assignment Analysis before running the EDA Netlist Writer
CAUSE: Analysis & Synthesis or I/O Assignment Analysis was not run successfully with the specified top-level entity name before running the EDA Netlist Writer.
ACTION: Before running the EDA Netlist Writer, you need to perform one of the following:
- Run Analysis & Synthesis to generate:
- an EDA functional RTL simulation netlist file
- Run I/O Assignment Analysis to generate:
- an IBIS file
- a HSPICE file, or
- a BSDL file
- Run full compilation to generate one or more of the following:
- an EDA gate level simulation netlist file
- an EDA timing analysis file
- a formal verification output file
- a physical synthesis output file
- a board-level symbol file
- a board-level timing analysis file