ID:199055 Can't generate files for Synopsys PrimeTime timing analysis tool because VHDL format is not supported if the Timing Analyzer is selected as the timing analysis tool in the current device family

CAUSE: The Synopsys PrimeTime timing analysis tool settings specify VHDL as the output format. However, the Timing Analyzer does not support VHDL format for Synopsys PrimeTime timing analysis tool in the current device family.

ACTION: If you want to use Synopsys PrimeTime timing analysis tool as the EDA timing analysis tool in the current device family, switch to Verilog format.