ID:20180 VCD file timestamps are not in sequential order on line <name>

CAUSE: The Verilog Value Change Dump File (.vcd) does not conform to IEEE Std 1364-2001. All timestamps must be in sequential order. This error can sometimes be caused by failure to close the VCD file in the simulator used for its creation.

ACTION: Quit the simulation in which the VCD file was generated or correct the input VCD file.