ID:13078 The tri-state buffer "<name>" directly or indirectly feeds its own output enable.

CAUSE: The specified tri-state buffer directly or indirectly feeds its own output enable. The behavior of such a loop is undefined, hence such a loop is not legal. This can happen if the tri-state buffer has its output enable signal connected either to itself or to the same bidirectional pin that it feeds. For example, the following Verilog design gives this error:

		module test1 (data, bidir); 
		input data; 
		inout bidir; 
		wire tri_wire; 
		assign tri_wire = bidir; 
		assign bidir = tri_wire ? data : 1'bZ; 
		endmodule