ID:20445 The reference clock on PLL "<name>", which feeds an LVDS SERDES IP instance, is not driven by a clock pin from an IO bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.

CAUSE: PLLs driving LVDS SERDES interfaces should use dedicated reference clock pins from an IO bank. Using a different source, such as a global clock or PLL cascading can add extra jitter, and it has not been fully verified and characterized by Intel. It is therefore not guaranteed to meet its max data rate specification.

ACTION: Use a dedicated reference clock pin per PLL that drives an LVDS SERDES IP instance.