ID:275074 Width mismatch for port "<name>" with instance "<name>" of type <name> and signal "<name>". Design will not compile in VHDL.

CAUSE: You created a Graphic Design File (.gdf), but the dimensions of the signal feeding the specified port conflict. A two-dimensional signal cannot be connected to a single-dimensional port. Once the design is converted, the VHDL Design File will not compile.

ACTION: Correct the design so that the dimension and width is equal for the port and signal, and create the HDL design file again.