ID:18562 HPS DDR conduit is enabled but the HPS EMIF is not placed in IO bank 2K.

CAUSE: The Arria10 HPS EMIF IP component in QSYS is responsible for the proper HPS EMIF placement but Quartus detected that the HPS has the EMIF interface enabled and there is no HPS EMIF in the IO bank 2K. You might be missing to instantiate the HPS EMIF in your design or the HPS EMIF was misplaced.

ACTION: Contact your Intel FAE for help.