ID:176401 Can't place PLL <name> in location <name> -- input clocks of PLL driven by <number> clock signals -- exceeds maximum of <number> global signal(s)

CAUSE: You assigned the Global Signal option with a value other than OFF to the clock signals driving the specified phase-locked loop (PLL) or the input clocks to the PLL are not placed at a clock pin that can drive the PLL. However, the number of clock signals driving the PLL exceeds the specified maximum number of global signals that can drive the PLL. Click the + icon in the Messages window or the Messages section of the Report window to display details on the clock signals driving the PLL.

ACTION: Change the Global Signal assignment to a value of OFF for the clock signals driving the PLL and assign the clock signals to dedicated clock pin locations that can drive the PLL directly.