ID:176398 PLL <name> requires <number> external clock output pins using a differential I/O standard, but the maximum that are supported by any PLL is <number>

CAUSE: The specified phase-locked loop (PLL) needs to use the specified number of external clock output pins that use a differential I/O standard, but the external clock output pins exceed the maximum that are supported by any PLL on the device.

ACTION: Reduce the number of external clock outputs in the design.