ID:176162 Input clock pin of fast PLL <name>, which drives at least one non-DPA-mode SERDES, must be driven by a compensated input

CAUSE: The Fitter tried to place the specified fast PLL. However, the fast PLL drives at least one non-DPA-mode SERDES. As a result, the fast PLL input clock pin must be driven by a compensated input. The Fitter cannot place the specified fast PLL.

ACTION: Modify the design so that the fast PLL input clock pin is driven by a compensated input.