ID:176153 Fast PLL <name> drives DPA channels with <number> Mbps differential I/O data rate, but the target device <name> can support only <number> Mbps maximum differential I/O data rate for DPA channels

CAUSE: The specified fast PLL is driving dynamic phase alignment (DPA) channels with the specified differential I/O data rate. However, the target device can support only the specified maximum differential I/O data rate for DPA channels.

ACTION: Modify the design so that the differential I/O data rate is less than or equal to the specified maximum differential I/O data rate for DPA channels of the target device.