ID:176161 Can't place input clock pin <name> driving fast PLL <name> in non-compensated I/O location <name> -- fast PLL drives at least one non-DPA-mode SERDES

CAUSE: The Fitter tried to place the specified input clock pin that drives the specified fast PLL in the specified non-compensated I/O location. However, the fast PLL also drives at least one non-DPA-mode SERDES. As a result, the input clock pin must be placed in a compensated I/O location. The Fitter could not place the input clock pin.

ACTION: Modify the design so that the input clock pin is placed in a compensated I/O location.