ID:176716 inclk port of Clock Control Block "<name >" must be driven by <number > GPLL but is driven by <number > GPLLs.

CAUSE: The specified inclk port of the Clock Control Block is driven by the specified number of phase-locked loops (PLLs). The number of PLLs is more than the number of PLLs required to drive the inclk port. The Clock Control Block can only be driven by the specified number of PLLs.

ACTION: Modify your design, and then reduce the number of PLLs that drive the Clock Control Block to the specified number.