ID:16251 Invalid connection for core output enable signal associated with EMIF/PHYLite input pin <Pin name>. Connect the output enable port to GND or VCC, depending on your parameter configurations.

CAUSE: An output enable signal associated with the specified io_12_lane input-only pin must be connected to GND, or to VCC if the lane_db_pin_<>_oe_invert parameter is set, however the output enable port is not connected correctly in your design.

ACTION: Connect the output enable port (oe_from_core) to GND on the specified input-only pin on the io_12_lane atom. If the lane_db_pin_<>_oe_invert parameter is set, connect the output enable port to VCC.