ID:18090 External memory and PHYLite interfaces must share common clock and reset signals when constrained to the same I/O column. The following conflicting signals were found:

CAUSE: The external memory or PHYLite interfaces in the same I/O column are driven by different clock or reset signals.

ACTION: Make sure that external memory or PHYLite interfaces constrained to the same I/O column use the same clock/reset signal.