ID:181051 DQS Group fed by DQS I/O pin "<cell>" might not function correctly on the selected Stratix V ES Device

CAUSE: Your design contains a memory interface configuration that might not function correctly in the selected Stratix V Engineering Sample (ES) device with the current I/O pin placement.

ACTION: All Stratix V production devices function correctly with the current pin placement. If you did not implement your design with ES devices, change the targeted device to a non-ES part. You can avoid this problem by constraining some I/Os to different locations in the FPGA. For a list of impacted I/Os, consult the sub-messages. For further assistance on how to resolve this issue, contact Intel technical support directly.