ID:15911 Input port <text> of PLL "<name>" must be driven by the <text> output of the same PLL.

CAUSE: The specified PLL is used to compensate an LVDS clock network. In this case, the fbin input of the specified PLL must be driven by the fbout output of the same PLL.

ACTION: Make sure the fbin input and the fbout output of the specified PLL are connected properly.