ID:15543 PLL "<name>" has counter <name> being used by multiple clock outputs <names>

CAUSE: You restricted the specified counter for specified clock outputs of the specified PLL with the Force PLL Output Counter logic option (that is, the PLL_FORCE_OUTPUT_COUNTER option is used to specify the counter used in the Quartus Prime Settings File (.qsf)). Only one counter can be used for each clock output.

ACTION: Change counter assignments so each clock output is assigned a different counter.