ID:15542 PLL "<name>" has output clock "<name>" restricted to use counter <name>, but the counter requires cascaded inputs from counter <name>, which is already used by clock output <name>

CAUSE: You restricted the specified counter to be used for the specified clock output of the specified PLL with the Preserve PLL Counter Order logic option (that is, the PRESERVE_PLL_COUNTER_ORDER option is turned on in the Quartus Prime Settings File (.qsf)). In order to implement the requested multiply and divide ratios for the clock output, cascaded counters must be used; however, the required cascaded counter is already being used by another clock output.

ACTION: Change the counter restrictions, change the clock output ordering so that no conflicts occur between cascaded counters of different clock outputs, or change the multiply and divide ratios so that cascaded counters are not needed. You can also modify the counters so they are not restricted to be used for the clock output ports (or turn off the Preserve PLL Counter Order logic option) and allow the Compiler to choose the counters automatically instead.