ID:15516 clk0 or clk1 output port of fast PLL "<name>" must drive only a clock input port of a SERDES receiver or transmitter

CAUSE: The clk0 or clk1 port of the specified fast PLL drives logic other than the clock input port of a SERDES receiver or transmitter or does not drive any logic. The clk0 or clk1 port must drive only a clock input port of a SERDES receiver or transmitter. This error usually occurs when you instantiate a megafunction directly in a text file rather than using the MegaWizard Plug-In Manager .

ACTION: Modify the design so that the clk0 or clk1 port of the fast PLL drives a clock input port of a SERDES receiver or transmitter.