ID:15990 phasectrlin[<number>] input port of OUTPUT_PHASE_ALIGNMENT primitive "<name>" can be unconnected or driven by only the dqsoutputphasesetting[<number>] output port of a DQS config primitive if the USE_PHASECTRL_CLK parameter is set to FALSE

CAUSE: The phasectrlin input port of the specified OUTPUT_PHASE_ALIGNMENT primitive is driven by an illegal source.

ACTION: Check the design and make sure that the specified phasectrlin input port either is driven by the dqsoutputphasesetting output port of a DQS configuration or is unconnected.