ID:21002 The enaoutputcycledelay input of output phase alignment primitive "<name>" must be driven by enaoctcycledelaysetting output of a DQS configuration primitive when ADD_OUTPUT_CYCLE_DELAY parameter is set to "dynamic" and OPERATION_MODE parameter is set to either "rtena" or "extended_rtena"

CAUSE: The enaoutputcycledelay input of the specified output phase alignment primitive is driven by an illegal source.

ACTION: Check the design and make sure that the specified enaoutputcycledelay input is driven by the enaoctcycledelaysetting output of a DQS configuration primitive. Alternatively, you can change the values of the ADD_OUTPUT_CYCLE_DELAY and the OPERATION_MODE parameters.