ID:21044 The resyncinputphaseinvert output of DQS configuration primitive "<name>" can only drive phaseinvertctrl input of an input phase alignment primitive or an I/O clock divider primitive.

CAUSE: The resyncinputphaseinvert output of the specified DQS configuration primitive has an illegal connection.

ACTION: Check the design and make sure that if the specified resyncinputphaseinvert output is connected, it is connected to the phaseinvertctrl input of an input phase alignment primitive of an I/O clock divider primitive.