ID:21116 PLL Signal "<name>" feeds the inclk[<number>] input port of GXB transceiver PLL "<name>" through a clock control

CAUSE: The specified clock input port of the specified gigabit transceiver block (GXB) transceiver PLL is fed by the specified PLL signal through a clock control.

ACTION: Modify the design so that the clock input port of the specified GXB transceiver PLL is directly fed by the cascaded source PLL.