ID:16586 When signal ENA0 or ENA1 is connected in WYSIWYG RAM primitive "<name>" "<name>", port "<name>" also must be connected. Connect the specified clock port.

CAUSE: For the specified WYSIWYG RAM primitive, signal ENA0 or ENA1 is connected, but port clk0 or clk1 is not connected, however, the clock port must be connected when signal ENA0 or ENA1 is connected.

ACTION: Connect the specified clock port.