ID:18863 When signal ENA0 connected in WYSIWYG RAM primitive "<name>" clk0_input_clock_enable and clk0_output_clock_enable cannot set to none.

CAUSE: For the specified WYSIWYG RAM primitive, signal ENA0 is connected, clk0_input_clock_enable and clk0_output_clock_enable port must connect ena0.

ACTION: Connect the specified clock port.