ID:15534 PLL clock output <name> feeding <name> has illegal output frequency of <number> that must be <text>

CAUSE: You specified the MULTIPLY_BY and DIVIDE_BY parameter values of the output frequency for the specified PLL output port. However, the output frequency must be in the specified frequency range when feeding the specified destination.

ACTION: Modify the design so that the MULTIPLY_BY and DIVIDE_BY parameter values of the specified PLL clock output are in the required range.