ID:15359 DSP block slice contains WYSIWYG primitive "<name>" that has <number> clk and ce pairs -- WYSIWYG primitive "<name>" cannot have more than <number> clk and ce pairs

CAUSE: The specified WYSIWYG primitive of a DSP block slice has too many clk and ce pairs. The WYSIWYG primitive cannot have more than the specified number of clk and ce pairs.

ACTION: If you are using an EDA tool, contact the technical support for the EDA tool regarding this message. For further assistance contact Intel Technical Support by creating a Service Request at www.altera.com/mysupport.