ID:16599 All second-stage pipeline registers must share the same clock source for DSP block WYSIWYG primitive "<name>". Change your design so the second-stage pipeline registers feeding the DSP block WYSIWYG prmitive share the same clock source.

CAUSE: The second-stage pipeline registers in your design do not share the same clock source for the specified DSP block WYSIWYG primitive, however, all second-stage pipeline registers must share the same clock source.

ACTION: Change your design so the second-stage pipeline registers feeding the DSP block WYSIWYG primitive share the same clock source.