ID:15693 pllcalibrateclk input port of Clock Delay Control Calibration block "<name>" is fed by clock output of PLL "<name>", while its plldataclk input port is fed by clock output port of PLL "<name>"

CAUSE: The pllcalibrateclk and plldataclk input ports of the specified Clock Delay Control Calibration blocks are fed by the clock output ports of the two specified PLLs. The pllcalibrateclk and plldataclk input ports of a Clock Delay Control Calibration block must always be fed by the clock output ports of the same PLL.

ACTION: Modify the design so that the clock output ports of the same PLL feeds the pllcalibrateclk and plldataclk input ports of the specified Clock Delay Control Calibration block.