ID:14265 DSP block output WYSIWYG primitive "<name>" uses inverted outputs, but inverted outputs are not supported in the target family

CAUSE: The specified DSP block WYSIWYG primitive was originally created for a different family and uses inverted outputs, but inverted outputs are not supported in the target family's DSP block. As a result, this WYSIWYG primitive cannot be remapped to the target family.

ACTION: Do not use DSP blocks with inverted outputs. For example, do not use Verilog Quartus Mapping File (.vqm) files containing DSP blocks with inverted outputs. To prevent use of output programmable inversion, modify the original design that generated the VQM file to use only positive logic from the specified DSP block to its destinations; or set the instance assignment REMOVE_REDUNDANT_USER_CELLS = OFF on the inverted logic cells that were absorbed into the DSP block output during fitting.