ID:20742 WYSIWYG RAM primitive "<name>" must have the "<name>" port and "<name>" port connected to the identical clock source with identical clock unateness.

CAUSE: In the current design, you have connected both clk0 and clk1 ports to either non-identical clock source or non-identical clock unateness, which is not allowed.

ACTION: Modify the design to ensure clk0 and clk1 ports are connected to the identical clock source with identical clock unateness.