Bring out device-wide set/reset signals as ports

Directs the EDA Netlist Writer to add the devpor, devclrn, and devoe signals in the design as input ports in the top-level design hierarchy in the VHDL Output File (.vho) Definition or Verilog Output File (.vo) Definition output netlist for the project. This option is useful when you want to create a test-bench and you want to redefine signals as ports.