Optimize IOC Register Placement for Timing logic option
A logic option that controls whether the Fitter optimizes I/O pin timing by automatically packing registers into I/O pins to minimize pin-to-register and register-to-pin delays. If you turn on this option, you must also set the Optimize hold timing option to All paths on the Fitter Settings page of the Settings: dialog box .
This option is available for all Intel devices.
Scripting Information |
Keyword:: optimize_ioc_register_placement_for_timing Settings: on | off *default |