RES-30008: External Reset Signals Incorrectly Synchronized

This rule applies when the external reset is synchronized but fails to adhere to the guidelines of cascaded registers triggered by the same clock edge.

An external reset synchronized with a single register is not considered complete as it leaves probability of metastability in the reset domain. Hence, two cascaded registers are required.

The following image shows an example of an incorrectly synchronized external reset:

Figure 1. Incorrectly Synchronized External Reset

Similarly, when cascaded synchronization registers are triggered on different clock edges, the risk is higher that the second register does not have enough time to resolve the metastable output from the first register. Hence, both cascading registers should be triggered on the same clock edges. The following image shows an example of an incorrectly synchronized external reset:

Figure 2. Incorrectly Synchronized External Reset

Recommendation

Follow these guidelines for the synchronization of an external reset (which is a primary input that is used as a reset signal):

  • Synchronize the external reset with two cascading registers.
  • Trigger the cascading registers on the same clock edge.

The following image shows an example of a correctly synchronized external reset:

Figure 3. Correctly Synchronized External Reset

Severity

High

Stage

Analysis and Elaboration

Device Family

  • Intel® Cyclone® 10 GX
  • Intel® Arria® 10