FLP-40001: Congested Placement Region
High utilization, localized to a certain region, may lead to congestion
and long routing detours having adverse impact on timing of critical nets in the
region.
This usually is caused by one or more of the following sub-optimal floorplanning decisions:
- Pin planning
- Smaller Logic Lock region for the associated logic partition or partial reconfiguration (PR) partitions.
- Incorrect placement of Logic Lock region.
- Sub-optimal shape of Logic Lock region.
Parameter
| Name | Default Value | Description |
|---|---|---|
| Region_Placement_Threshold | 70% |
Reports a violation for placement regions that have placement congestion higher than the value specified in this parameter. |
Recommendation
Review whether the Logic Lock region is sufficiently large enough to contain the associated logic, or if it needs to be moved or reshaped to follow connectivity of the interface logic.
Severity
Low
Stage
Place, Finalize
Device Family
- Intel® Stratix® 10
- Intel® Agilex™
- Intel® Arria® 10
- Intel® Cyclone® 10 GX