ACD-30023: Data Bits Are Not Synchronized When Transferred Between Asynchronous Clock Domains

In a design, data bits that are transferred between asynchronous clock domains should be synchronized.

Synchronize single-bit data bits individually using cascaded registers that are triggered on the same clock edge. For data bits belonging to multiple-bit data, use a handshake protocol to guarantee that all bits of the data bus are stable when the receiving clock domain samples the bus.

The following image shows an example of data bits that are transferred between asynchronous clock domains that are not synchronized:

Figure 1. Transfer of Data Bits Between Asynchronous Clock Domains Example

Recommendation

Consider the following:

  • If data bits belong to a single-bit data, following the below guidelines can help you prevent metastability problems during synchronization of data bits:
    • Synchronize each data bit with the appropriate number of cascading registers in the receiving asynchronous clock domain.
    • Trigger cascading registers on the same clock edge.
    • Avoid using logic between the output of the transmitting clock domain and the cascaded registers in the receiving asynchronous clock domain.
  • If data bits belong to multiple-bit data, use a handshake protocol to guarantee that all bits of the data bus are stable when the receiving clock domain samples from the bus.
  • If you use a handshake protocol, only the data bits that act as REQ (Request) and ACK (Acknowledge) signals should be synchronized. Data bits that belong to multiple-bit data need not be synchronized. You can ignore the violation on data bits that use a handshake protocol.

The following image shows an example of the transfer of data bits between asynchronous clock domains where only the REQ and ACK signals are synchronized:

Figure 2. Transfer of Data Bits Between Asynchronous Clock Domains Example

Severity

High

Stage

Analysis and Elaboration

Device Family

  • Intel® Arria® 10
  • Intel® Cyclone® 10