Show Instantiation Template (Generate Menu) (Platform Designer)

Provides the top-level HDL definition of the Platform Designer system in either Verilog HDL or VHDL. This tab also displays VHDL component declarations.

If the system is not the top-level module in the Intel® Quartus® Prime project, you can copy the HDL example and paste it into the top-level HDL file that instantiates the Platform Designer system,

To generate a the instantiation template, click Generate > Show Instantiation Template.