Glossary 8B/10B encoder/decoder Definition Assignment & Configuration File (.acf) Definition Altera Hardware Description Language (AHDL) Definition Adaptive Logic Module (ALM) Definition Adaptive Look-Up Table (ALUT) Definition Intel FPGA IP Core Partner Program (AMPP) Definition Altera Programming Unit (APU) Definition arithmetic operator Definition arithmetic expressions (AHDL) Definition Arria II Device Family Definition Arria V Device Family Definition Intel Arria 10 Device Family Definition Active Serial configuration scheme (AS) Definition Support Center Atom Netlist File (.atm) Definition atom Definition Auxiliary Transmit (ATX) PLL Definition Avalon Streaming Sink Interface Definition Avalon Streaming source port Definition Avalon Streaming Component Specific Signals Definition Avalon Memory-Mapped Interface Definition Avalon Interface Definition Avalon Streaming Interface (Avalon-ST) Definition Avalon-ST configuration scheme (AVST) Definition back-annotation Definition Backpressure Definition version-compatible database files Definition Block Design File (.bdf) Definition BGA Definition BIT0 option Definition n-bit configuration Definition Backus-Naur Form (BNF) Definition Boundary-Scan Description Language File (.bsd) Definition Block Symbol File (.bsf) Definition bypass path Definition ByteBlasterMV Cable Definition Intel FPGA Parallel Port Cable Definition C4, C8, C16 interconnect Definition Chain Description File (.cdf) Definition common flash interface (CFI) Definition Configuration Flash Memory (CFM) Definition channel Definition channel aligner Definition clear box feature Definition Clock Control Block Definition multiclock network Definition clock skew Definition Component Declaration File (.cmp) Definition configuration memory space Definition Conversion Setup File (.cof) Definition collection Definition component Definition COM port Definition configuration device Definition cyclic redundancy check (CRC) Definition clock recovery unit (CRU) Definition Comma-Separated Value File (.csv) Definition Custom Region Definition Compressed Vector Waveform File (.cvwf) Definition Cyclone IV Definition Cyclone V Device Family Definition Cyclone 10 GX Device Definition Cyclone 10 LP Device Definition license file (license.dat) data arrival time Definition data realigner Definition data required time Definition database files Definition data skew Definition double data rate (DDR) Definition decimal Definition delay chain Definition delimiter Definition design files Definition design Definition design entity Definition design unit Definition device Definition device assignment Definition device migration Definition device option Definition differential I/O standards Definition differential I/O pin Definition DIP Definition direct link Definition delay-locked loop (DLL) Definition DM pin Definition dynamic phase alignment (DPA) Definition Design Protocol File (.dpf) Definition DQ I/O Definition DQS I/O Definition memory segment Definition DSP block Definition DSP block balancing Definition dual-purpose pins Definition Dual-regional clock Definition dual I/O feedback Definition dual-range group or bus name Definition dynamic phase aligner Definition embedded cell (EC) Definition edge Definition EDIF Input File (.edf) Definition EDIF Definition EEPROM Definition Signal Tap Logic Analyzer Definition elaboration Definition electromigration Definition embedded multiplier block enhanced PLL Definition entity Definition Intel FPGA Ethernet Cable Definition Intel FPGA Ethernet Cable Definition evaluated function Definition expander product term Definition device family Definition fan-in and fan-out fast PLL Definition Fast Region Definition FLEX Chain File (.fcf) file name extension Definition file types Definition FineLineBGA, Micro FineLine BGA, and UltraFineLineBGA Definition Passive Serial chain Definition floorplan Definition fmax Definition FPGA Xchange-Format File (.fx) Definition Fractional PLL Definition floating-point multiplier Definition Fast Passive Parallel configuration scheme Definition Intel Quartus Prime Message Flag Rule File (.frf) Definition functional simulation Definition gated clock signal Definition gate primitive Definition Graphic Design File (.gdf) Definition generic Definition glitch Definition global clock Definition global signal Definition GND Definition gray code Definition group Definition gigabit transceiver block (GXB) Definition GXB transmitter PLL & GXB receiver PLL Definition hard logic function Definition hexadecimal Definition Hexadecimal (Intel-Format) File (.hex) Definition Hexadecimal (Intel-Format) Output File (.hexout) Definition hierarchical node name Definition th (clock hold time) Definition HSPICE Simulation Deck File (.sp) Definition HTML-Format Report File (.htm) Definition Component Description File (_hw.tcl) IBIS Output File (.ibs) Definition in-circuit reconfigurability (ICR) Definition identifier Definition AHDL Include File (.inc) Definition Input Transition Time timing assignment logic option insertion point Definition instance Definition interquad clock Definition I/O bank Definition I/O element Definition I/O cell Definition I/O standards Definition I/O Pin State File Definition (.ips) IP Index File (.ipx) In System Configuration File (.isc) Definition in-system programmability (ISP) Definition Jam File (.jam) Definition Jam Byte Code File (.jbc) Definition JTAG Debug Information File (.jdi) Definition JTAG Indirect Configuration File (.jic) Definition J-lead Definition JTAG boundary-scan testing Definition JTAG chain Definition keeper Definition keyword Definition Logic Array Block (LAB) Definition Logic Analyzer Interface File (.lai) Definition Logic Analyzer Interface Definition Late Clock Latency timing assignment Definition logic cell Definition design library Definition Library Mapping File (.lmf) Definition local routing Definition location Definition logical operator Definition logic element Definition logic function Definition logic levels Definition Logic Lock Region Definition logic primitive Definition library of parameterized modules (LPM) Definition LUT chain interconnect Definition M10K memory block Definition M144K memory block Definition M20K memory block Definition M9K memory block Definition macrocell Definition macrofunction Definition Memory Map File (.map) Definition mapper Definition mapper table Definition MAX II Definition MAX V Definition MUX Configuration File (.mcf) Definition Mealy state machine Definition M-RAM Definition Licensed Intel FPGA IP Definition Intel FPGA IP Definition memory bit Definition memory element (Verilog HDL) Definition memory word Definition metastable state or metastability Definition Memory Initialization File (.mif) Definition migration Definition migration device Definition Minimum tco (clock to output delay) Definition Minimum tpd (pin-to-pin delay) Definition MLAB Definition multilevel clock Definition Mnemonic Table Definition module Definition Moore state machine Definition multipurpose PLL Definition Mask Settings File (.msf) Definition multiplier block Definition multiplying operator Definition name characters Definition nesting Definition net Definition node Definition node name Definition node type Definition on-chip termination (OCT) Definition octal Definition operator Definition Intel FPGA IP Evaluation Mode Definition operand Definition oscillation Definition other files or project-related files Definition package Definition pad Definition parallel port Definition parallel expanders Definition parameter Definition Parameter assignments Definition parameterized function Definition parameterized module Definition PartMiner edaXML-Format File (.xml) Definition part-select Definition pattern detector Definition parallel flash loader (PFL) scheme Definition PGA Definition Intel Technical Support Definition Programmable Interconnect Array (PIA) Definition pin Definition Pin-Out File (.pin) Definition Phase-Locked Loop (PLL) Definition Partial-Mask SRAM Object File (.pmsf) Definition Programmer Object File (.pof) Definition port Definition Early Power Estimator file Definition Programmable Power Technology Tiles Definition Pin Planner File (.ppf) Definition programming files Definition primitive Definition Procedural Assignment Definition process Definition product term Definition programming hardware Definition project Definition propagation delay Definition Function Prototype Definition Intel Quartus Prime Archive File (.qar) Definition Intel Quartus Prime Archive Log File (.qarlog) Definition Intel Quartus Prime Default Settings File (.qdf) Definition quad data rate II (QDRII) SRAM Definition PQFP Definition Intel Quartus Prime IP File (.qip) Definition Intel Quartus Prime Message File (.qmsg) Intel Quartus Prime Project File (.qpf) Definition Intel Quartus Prime Settings File (.qsf) Definition Platform Designer Definition Platform Designer System File (.qsys) Definition quad Definition Intel Premier Support website Definition Intel Quartus Prime User-Defined Device File (.qud) Definition quiet high definition quiet low definition Intel Quartus Prime Workspace File (.qws) Definition Intel Quartus Prime Exported Partition File (.qxp) Definition R4, R8, R24 interconnect Definition race condition Definition radix Definition RAM Definition RAM block Definition range Definition rate matcher Definition Raw Binary File (.rbf) Definition receiver channel-to-channel skew (RCCS) Definition Routing Constraints File (.rcf) Definition register Definition regional clock Definition Register Duplication and Register Retiming Node Naming Scheme regular expressions Definition region Definition register chain interconnect Definition register packing Definition relational operator Definition remote update block Definition remote/local update difference file Definition Number of Source Nodes to Report per Destination Node timing assignment Definition resource assignment Definition revision description file Definition ROM Definition register pipelining Definition Raw Programming Data File (.rpd) Definition Text-Format Report File (.rpt) Definition RQFP Definition receiver input skew margin (RSKM) Definition rubberbanding Definition Signal Activity File (.saf) Definition SameFrame device Definition sampling window Definition scalar (Verilog HDL) Definition Synopsys Design Constraints File (.sdc) Definition single data rate (SDR) Definition secondary input Definition segmented buffer Definition sequential group (or bus) name Definition SERDES Definition Passive Serial configuration scheme (PS) Definition setup relationship Definition shared expanders and shareable expanders Definition Run All Timing Analyses timing assignment Definition signal margin definition In-Socket Programming mode Definition Intel Quartus Prime Simulation IP File (.sip) Definition slack Definition state machine Definition State Machine File (.smf) Definition snapshot Definition SRAM Object File (.sof) Definition SOIC Definition source-synchronous circuitry Definition vector source files Definition Signal Probe Definition Sources and Probes File (.spf) Definition Intel Quartus Prime Message Suppression Rule File (.sff) Definition simultaneous switching noise (SSN) definition Stamp model files Definition state name Definition state transition Definition state Definition state bit Definition stderr Definition stdout Definition Signal Tap File (.stp) Definition Stratix IV Definition Stratix V Definition subdesign Definition SystemVerilog Design File (.sv) Definition Serial Vector Format File (.svf) Definition SystemVerilog Output File (.svo) Symbol File (.sym) Definition symbolic name Definition Symbol Definition symbol name Definition synthesized logic cells Definition synchronizer Definition target Definition test bench file Definition Vector Table Output File (.tbl) Definition transmitter channel-to-channel skew (TCCS) Definition tch (minimum clock high time) Definition Tcl Script File (.tcl) Definition tcl (minimum clock low time) Definition tco (clock to output delay) Definition Text Design File (.tdf) Definition Text Design Output File (.tdo) Definition ternary operator Definition timing requirements and constraints Definition time unit Definition title block Definition title block section Definition Token File (ted.tok) Definition top-level design entity Definition tpd (pin-to-pin delay) Definition TQFP Definition trigger Definition trigger position Definition tsu (clock setup time) Tabular Text File (.ttf) Definition time unit interval (TUI) Definition Tab-Separated Value File (.txt) Definition type (VHDL) Definition tzx (Clock-to-low-impedance time) Definition UFM Definition Intel FPGA Download Cable Definition Verilog Design File (.v) Definition variable Definition VCC Definition Value Change Dump File (.vcd) Definition vectors (simulation) Definition Verilog HDL Definition VHDL Design File (.vhd) Definition VHDL Definition VHDL Output File (.vho) Definition VHDL Test Bench File (.vht) Definition VIHmin (DC) definition VILmax (DC) definition virtual pins Definition VITAL (VHDL Initiative Toward ASIC Libraries) Definition parameter (Verilog HDL) Definition vector (Verilog HDL) Definition Verilog Output File (.vo) Definition VREF group Definition Verilog Test Bench File (.vt) Definition Verilog Quartus Mapping File (.vqm) Definition Vector Waveform File (.vwf) Definition waveform files Definition channel width Definition wildcard characters Definition wire loop Definition word aligner Definition Waveform Settings File (.wsf) Definition Intel FPGA website Definition WYSIWYG primitive Definition XGMII state machine Definition XML files Definition Cross-Reference File (.xrf) Definition