ID:20083 Second pipeline register for DSP block WYSIWYG primitive "<atom name>" can only be enabled when (1) Both Pre-adder and Internal coefficient feature are not used but both input register and output register are used, OR (2) Input register, input pipeline register and output register are used.
CAUSE: Illegal clock enable parameter configuration of second pipeline registers for the specified DSP block WYSIWYG primitive"
ACTION: Correct the clock enable parameter of the specified second pipeline register.