ID:20082 Input pipeline register for DSP block WYSIWYG primitive "<atom name>" can only be enabled when (1) Pre-adder and/or Internal coefficient feature and input register and output register are used, OR (2) input register, second pipeline register and output register are used.
CAUSE: Illegal clock enable parameter configuration of input pipeline registers for the specified DSP block WYSIWYG primitive"
ACTION: Correct the clock enable parameter of the specified input pipeline register.