ID:16693 When Forwarding Logic is exercised, port "<name>" and "<name>" of "<name>" WYSIWYG RAM primitive must be connected to the identical clock source with identical clock unateness.

CAUSE: In the current design, you have connected both clk1 and clk0 ports to either non-identical clock source or non-identical clock unateness, which is not allowed in the hardware.

ACTION: Modify the design to by connect clk0.