Place Stage Reports

The Place stage reports describe all device resources the Fitter allocates during logic placement, as well as use of Logic Lock regions and global and other fast signals.
Figure 1. Place Stage Reports

Global Signal Visualization Report

In addition, for Intel® Stratix® 10 designs, you can access the Global Signal Visualization report to view global signal routing and overall clock sector utilization in an interactive heat-map. Use this data to quickly review how the Fitter constrains clock regions to device sectors. View global clock tree implementation details and assess capacity to add more global signals to the design. In cases of clock tree synthesis errors, the report can also show targeted regions for failing signals, and competing signals that are contributing to routing congestion.

Filter the display to Show Routing Utilization and Show Sector Utilization. You can search for Signal Names, and then click the signal names to display its properties. Right-click the Signal Names to Locate Node in Chip Planner and various other tools.

Figure 2. Heat-Map in Global Signal Visualization Report